| Summary: | The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage (V<sub>DD</sub>). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at L<sub>G</sub> = 13 nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional V<sub>DD</sub>. Also, P-TFET current-drive is between 1× to 0.5× of N-TFET, depending on choice of I<sub>OFF</sub> and V<sub>DD</sub>. There are many challenges to realizing TFETs in products, such as the requirement of high quality III-V materials and oxides with very thin body dimensions, and the TFET's layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.
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