Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors
This work introduces three novel chaotic map circuits. Two of the map circuits use two <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-channel and one <inline-formula> <tex-math notation="LaTeX">$n$ </tex-math>...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2023-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10167651/ |
| _version_ | 1827908307877101568 |
|---|---|
| author | Maisha Sadia Partha Sarathi Paul Md. Sakib Hasan |
| author_facet | Maisha Sadia Partha Sarathi Paul Md. Sakib Hasan |
| author_sort | Maisha Sadia |
| collection | DOAJ |
| description | This work introduces three novel chaotic map circuits. Two of the map circuits use two <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-channel and one <inline-formula> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula>-channel silicon-on-insulator (SOI) four-gate transistor (G <sup>4</sup>FET) while the third design uses two <inline-formula> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula>-channel and one <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-channel G <sup>4</sup>FET. The multi-gate structure of G <sup>4</sup>FET is leveraged to obtain four independent bifurcation parameters in the chaotic map with a simple three-transistor design. A chaotic oscillator design is proposed using this discrete-time chaotic map circuit, and the chaotic behavior is evaluated using bifurcation plot, Lyapunov exponent (LE), Correlation coefficient, Shannon entropy, and Stability analysis. The application of this multi-parameter chaotic oscillator is presented in a chaos-based reconfigurable logic gate, and the significant expansion of parameter design space compared to existing single-gate transistor-based maps is also demonstrated. Finally, a simple extension scheme for developing multi-dimensional robust chaotic map with even larger parameter space is presented and verified with specific instances of 2-D and 3-D maps. |
| first_indexed | 2024-03-13T01:21:01Z |
| format | Article |
| id | doaj.art-0fc2f29083cf4687ae11e2e4f4e86ec1 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-13T01:21:01Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-0fc2f29083cf4687ae11e2e4f4e86ec12023-07-04T23:00:30ZengIEEEIEEE Access2169-35362023-01-0111647826479510.1109/ACCESS.2023.329013310167651Compact Analog Chaotic Map Designs Using SOI Four-Gate TransistorsMaisha Sadia0https://orcid.org/0000-0003-1854-8739Partha Sarathi Paul1https://orcid.org/0000-0002-8868-5854Md. Sakib Hasan2https://orcid.org/0000-0002-4792-6236Department of Electrical and Computer Engineering, The University of Mississippi, Oxford, MS, USADepartment of Electrical and Computer Engineering, The University of Mississippi, Oxford, MS, USADepartment of Electrical and Computer Engineering, The University of Mississippi, Oxford, MS, USAThis work introduces three novel chaotic map circuits. Two of the map circuits use two <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-channel and one <inline-formula> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula>-channel silicon-on-insulator (SOI) four-gate transistor (G <sup>4</sup>FET) while the third design uses two <inline-formula> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula>-channel and one <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-channel G <sup>4</sup>FET. The multi-gate structure of G <sup>4</sup>FET is leveraged to obtain four independent bifurcation parameters in the chaotic map with a simple three-transistor design. A chaotic oscillator design is proposed using this discrete-time chaotic map circuit, and the chaotic behavior is evaluated using bifurcation plot, Lyapunov exponent (LE), Correlation coefficient, Shannon entropy, and Stability analysis. The application of this multi-parameter chaotic oscillator is presented in a chaos-based reconfigurable logic gate, and the significant expansion of parameter design space compared to existing single-gate transistor-based maps is also demonstrated. Finally, a simple extension scheme for developing multi-dimensional robust chaotic map with even larger parameter space is presented and verified with specific instances of 2-D and 3-D maps.https://ieeexplore.ieee.org/document/10167651/Chaoschaotic oscillatordiscrete chaotic mapG4FEThardware securitynonlinear dynamics |
| spellingShingle | Maisha Sadia Partha Sarathi Paul Md. Sakib Hasan Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors IEEE Access Chaos chaotic oscillator discrete chaotic map G4FET hardware security nonlinear dynamics |
| title | Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors |
| title_full | Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors |
| title_fullStr | Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors |
| title_full_unstemmed | Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors |
| title_short | Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors |
| title_sort | compact analog chaotic map designs using soi four gate transistors |
| topic | Chaos chaotic oscillator discrete chaotic map G4FET hardware security nonlinear dynamics |
| url | https://ieeexplore.ieee.org/document/10167651/ |
| work_keys_str_mv | AT maishasadia compactanalogchaoticmapdesignsusingsoifourgatetransistors AT parthasarathipaul compactanalogchaoticmapdesignsusingsoifourgatetransistors AT mdsakibhasan compactanalogchaoticmapdesignsusingsoifourgatetransistors |