A dither‐less bit weight digital background calibration for bridge capacitor digital‐to‐analog converter successive approximation register analog‐to‐digital converters
Abstract The authors present a dither‐less background digital bit weights calibration method for split‐capacitor digital‐to‐analog converter (CDAC) successive approximation register (SAR) analog‐to‐digital converters (ADCs) to improve non‐linearities caused by capacitor mismatch and bridge‐capacitor...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2022-09-01
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| Series: | Electronics Letters |
| Online Access: | https://doi.org/10.1049/ell2.12581 |