A dither‐less bit weight digital background calibration for bridge capacitor digital‐to‐analog converter successive approximation register analog‐to‐digital converters
Abstract The authors present a dither‐less background digital bit weights calibration method for split‐capacitor digital‐to‐analog converter (CDAC) successive approximation register (SAR) analog‐to‐digital converters (ADCs) to improve non‐linearities caused by capacitor mismatch and bridge‐capacitor...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2022-09-01
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| Series: | Electronics Letters |
| Online Access: | https://doi.org/10.1049/ell2.12581 |
| Summary: | Abstract The authors present a dither‐less background digital bit weights calibration method for split‐capacitor digital‐to‐analog converter (CDAC) successive approximation register (SAR) analog‐to‐digital converters (ADCs) to improve non‐linearities caused by capacitor mismatch and bridge‐capacitor inaccuracy errors in a split‐CDAC. By using a digital pseudo‐random number (PN) generator and paired comparators with opposite offsets, a dither‐less background calibration quickly reaches the target signal‐to‐noise‐and‐distortion ratio (SNDR) within 5 × 104 samples for various process uncertainties. The simulated performance using a behavioural 6‐bit + 6‐bit ADC with 1‐bit redundancy for various random offset and capacitor mismatches shows that the SNDR increases from 45.7 to 65.7 dB after the calibration. |
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| ISSN: | 0013-5194 1350-911X |