Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems
The work describes the new architecture of a fixed-point arithmetic unit. It is based on the use of integer arithmetic operations for which the information about the scale of the processed numbers is contained in the binary code of the arithmetic instruction being executed. Therefore, this approach...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-05-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/10/1164 |