Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems
The work describes the new architecture of a fixed-point arithmetic unit. It is based on the use of integer arithmetic operations for which the information about the scale of the processed numbers is contained in the binary code of the arithmetic instruction being executed. Therefore, this approach...
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2021-05-01
|
| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/10/10/1164 |
| _version_ | 1797534146035187712 |
|---|---|
| author | Andrzej Przybył |
| author_facet | Andrzej Przybył |
| author_sort | Andrzej Przybył |
| collection | DOAJ |
| description | The work describes the new architecture of a fixed-point arithmetic unit. It is based on the use of integer arithmetic operations for which the information about the scale of the processed numbers is contained in the binary code of the arithmetic instruction being executed. Therefore, this approach is different from the typical way of implementing fixed-point operations on standard processors. The presented solution is also significantly different from the one used in floating-point arithmetic, as the decision to determine the appropriate scale is made at the stage of compiling the code and not during its execution. As a result, the real-time processing of real numbers is simplified and, therefore, faster. The described method provides a better ratio of the processing efficiency to the complexity of the digital system than other methods. In particular, the advantage of using the described method in FPGA-based embedded control systems should be indicated. Experimental tests on an industrial servo-drive confirm the correctness of the described solution. |
| first_indexed | 2024-03-10T11:26:30Z |
| format | Article |
| id | doaj.art-11d04407bbc143419b107d381e4d32b8 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T11:26:30Z |
| publishDate | 2021-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-11d04407bbc143419b107d381e4d32b82023-11-21T19:37:12ZengMDPI AGElectronics2079-92922021-05-011010116410.3390/electronics10101164Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded SystemsAndrzej Przybył0Faculty of Mechanical Engineering and Computer Science, Czestochowa University of Technology, 42-201 Częstochowa, PolandThe work describes the new architecture of a fixed-point arithmetic unit. It is based on the use of integer arithmetic operations for which the information about the scale of the processed numbers is contained in the binary code of the arithmetic instruction being executed. Therefore, this approach is different from the typical way of implementing fixed-point operations on standard processors. The presented solution is also significantly different from the one used in floating-point arithmetic, as the decision to determine the appropriate scale is made at the stage of compiling the code and not during its execution. As a result, the real-time processing of real numbers is simplified and, therefore, faster. The described method provides a better ratio of the processing efficiency to the complexity of the digital system than other methods. In particular, the advantage of using the described method in FPGA-based embedded control systems should be indicated. Experimental tests on an industrial servo-drive confirm the correctness of the described solution.https://www.mdpi.com/2079-9292/10/10/1164embedded systemsFPGAfixed-point arithmeticcontrol systems |
| spellingShingle | Andrzej Przybył Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems Electronics embedded systems FPGA fixed-point arithmetic control systems |
| title | Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems |
| title_full | Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems |
| title_fullStr | Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems |
| title_full_unstemmed | Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems |
| title_short | Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems |
| title_sort | fixed point arithmetic unit with a scaling mechanism for fpga based embedded systems |
| topic | embedded systems FPGA fixed-point arithmetic control systems |
| url | https://www.mdpi.com/2079-9292/10/10/1164 |
| work_keys_str_mv | AT andrzejprzybył fixedpointarithmeticunitwithascalingmechanismforfpgabasedembeddedsystems |