A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS
This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2023-06-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/14/7/1291 |
| _version_ | 1797588252988801024 |
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| author | Feitong Wu Xuan Guo Hanbo Jia Xiuheng Wu Zeyu Li Ben He Danyu Wu Xinyu Liu |
| author_facet | Feitong Wu Xuan Guo Hanbo Jia Xiuheng Wu Zeyu Li Ben He Danyu Wu Xinyu Liu |
| author_sort | Feitong Wu |
| collection | DOAJ |
| description | This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages charge pump amplifier topology is introduced, which doubles the Gain Bandwidth Product (GBW) without consuming additional power. To address the back-end ADC and background calibration, a multi-level dither strategy is employed, utilizing a new high-speed and low-cost uniform distribution pseudorandom code generator. The prototype ADC fabricated in 40 nm CMOS process achieves 68.24 dB SFDR up to Nyquist frequency with a sampling rate of 2 GS/s. Measurement results demonstrate a bandwidth exceeding 5 GHz, resulting in a Schreier FOMs of 152.4 dB. |
| first_indexed | 2024-03-11T00:49:31Z |
| format | Article |
| id | doaj.art-12d72fc7c15040998aa74ca9e69a5e34 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-11T00:49:31Z |
| publishDate | 2023-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-12d72fc7c15040998aa74ca9e69a5e342023-11-18T20:31:21ZengMDPI AGMicromachines2072-666X2023-06-01147129110.3390/mi14071291A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOSFeitong Wu0Xuan Guo1Hanbo Jia2Xiuheng Wu3Zeyu Li4Ben He5Danyu Wu6Xinyu Liu7Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaThis paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages charge pump amplifier topology is introduced, which doubles the Gain Bandwidth Product (GBW) without consuming additional power. To address the back-end ADC and background calibration, a multi-level dither strategy is employed, utilizing a new high-speed and low-cost uniform distribution pseudorandom code generator. The prototype ADC fabricated in 40 nm CMOS process achieves 68.24 dB SFDR up to Nyquist frequency with a sampling rate of 2 GS/s. Measurement results demonstrate a bandwidth exceeding 5 GHz, resulting in a Schreier FOMs of 152.4 dB.https://www.mdpi.com/2072-666X/14/7/1291single channelpipelined analog-to-digital converter(ADC)high linearitywide bandwidth |
| spellingShingle | Feitong Wu Xuan Guo Hanbo Jia Xiuheng Wu Zeyu Li Ben He Danyu Wu Xinyu Liu A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS Micromachines single channel pipelined analog-to-digital converter(ADC) high linearity wide bandwidth |
| title | A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS |
| title_full | A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS |
| title_fullStr | A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS |
| title_full_unstemmed | A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS |
| title_short | A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS |
| title_sort | 12 bit 2 gs s single channel high linearity pipelined adc in 40 nm cmos |
| topic | single channel pipelined analog-to-digital converter(ADC) high linearity wide bandwidth |
| url | https://www.mdpi.com/2072-666X/14/7/1291 |
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