A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM
This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to av...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2021-11-01
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| Series: | Sensors |
| Subjects: | |
| Online Access: | https://www.mdpi.com/1424-8220/21/22/7648 |