A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM
This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to av...
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MDPI AG
2021-11-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/21/22/7648 |
| _version_ | 1797508419007021056 |
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| author | Shi Zuo Jianzhong Zhao Yumei Zhou |
| author_facet | Shi Zuo Jianzhong Zhao Yumei Zhou |
| author_sort | Shi Zuo |
| collection | DOAJ |
| description | This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>251.6</mn></mrow></semantics></math></inline-formula> dB FoM. |
| first_indexed | 2024-03-10T05:04:43Z |
| format | Article |
| id | doaj.art-1362c36475e14fa1bfb6e948908c7f40 |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-10T05:04:43Z |
| publishDate | 2021-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-1362c36475e14fa1bfb6e948908c7f402023-11-23T01:27:21ZengMDPI AGSensors1424-82202021-11-012122764810.3390/s21227648A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoMShi Zuo0Jianzhong Zhao1Yumei Zhou2Smart Sensing R & D Centre, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaSmart Sensing R & D Centre, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaSmart Sensing R & D Centre, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaThis paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>251.6</mn></mrow></semantics></math></inline-formula> dB FoM.https://www.mdpi.com/1424-8220/21/22/7648SSPLLhybrid dual path looplow jitterlow power consumption |
| spellingShingle | Shi Zuo Jianzhong Zhao Yumei Zhou A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM Sensors SSPLL hybrid dual path loop low jitter low power consumption |
| title | A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_full | A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_fullStr | A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_full_unstemmed | A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_short | A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs<sub><i>rms</i></sub> Integrated Jitter and −251.6 dB FoM |
| title_sort | 0 8 v 5 3 5 9 ghz sub sampling pll with 196 5 fs sub i rms i sub integrated jitter and 251 6 db fom |
| topic | SSPLL hybrid dual path loop low jitter low power consumption |
| url | https://www.mdpi.com/1424-8220/21/22/7648 |
| work_keys_str_mv | AT shizuo a08v5359ghzsubsamplingpllwith1965fssubirmsisubintegratedjitterand2516dbfom AT jianzhongzhao a08v5359ghzsubsamplingpllwith1965fssubirmsisubintegratedjitterand2516dbfom AT yumeizhou a08v5359ghzsubsamplingpllwith1965fssubirmsisubintegratedjitterand2516dbfom AT shizuo 08v5359ghzsubsamplingpllwith1965fssubirmsisubintegratedjitterand2516dbfom AT jianzhongzhao 08v5359ghzsubsamplingpllwith1965fssubirmsisubintegratedjitterand2516dbfom AT yumeizhou 08v5359ghzsubsamplingpllwith1965fssubirmsisubintegratedjitterand2516dbfom |