| Summary: | We measure interface trap density near the conduction band edge and fixed oxide charge in commercial, packaged, 4H-SiC 1.2 kV planar Power MOSFETs. These traps determine the device threshold voltage, performance, and reliability. The subthreshold slope is used to extract interface trap density at the SiO<sub>2</sub>-SiC interface near the conduction band edge from three vendors, which varies from <inline-formula> <tex-math notation="LaTeX">$5.8\times 10 ^{12}$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$9.3\times 10 ^{12}$ </tex-math></inline-formula> cm<inline-formula> <tex-math notation="LaTeX">$^{-2}\cdot $ </tex-math></inline-formula>eV<sup>−1</sup>. Good agreement is obtained with threshold voltage measurements from 25°C to 150°C as devices with the highest interface trap densities exhibit the largest threshold voltage reduction over temperature. Fixed positive oxide charge, <inline-formula> <tex-math notation="LaTeX">$N_{ot}$ </tex-math></inline-formula>, balanced with interface traps and substrate doping, varies from <inline-formula> <tex-math notation="LaTeX">$3.3\times 10 ^{12}$ </tex-math></inline-formula> cm<sup>−2</sup> to <inline-formula> <tex-math notation="LaTeX">$3.7\times 10 ^{12}$ </tex-math></inline-formula> cm<sup>−2</sup>. At high temperatures, electrons captured in interface traps emit to the conduction band and lower the threshold voltage together with fixed oxide charges, which are as high as interface trap densities. Thus, device design should be considered for a suitable threshold voltage to ensure the device does not operate in a Normally-ON condition and to protect against gate voltage surges. Therefore, more focus on characterization and reduction of the interface trap density and fixed oxide charge is needed to enable further improvement in effective electron mobility of SiC MOSFETs.
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