Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories (block RAMs and registers). HLS tools allow e...

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Bibliographic Details
Main Authors: Giovanni Brignone, M. Usman Jamal, Mihai T. Lazarescu, Luciano Lavagno
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Cache
FPGA
high-level synthesis
memory management
Online Access:https://ieeexplore.ieee.org/document/9940270/

Internet

https://ieeexplore.ieee.org/document/9940270/

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