Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices
Abstract This paper comprehensively investigates the current distribution behaviours of paralleled SiC MOSFET devices under the parasitic coupling between gate and power loops. Three types of connection that are commonly adopted in actual applications, comprising common source connection (CSC), Kelv...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2022-08-01
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| Series: | IET Power Electronics |
| Online Access: | https://doi.org/10.1049/pel2.12292 |
| _version_ | 1828396431030878208 |
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| author | Haoran Zhang Junji Ke Jiaoyang Peng Peng Sun Zhibin Zhao |
| author_facet | Haoran Zhang Junji Ke Jiaoyang Peng Peng Sun Zhibin Zhao |
| author_sort | Haoran Zhang |
| collection | DOAJ |
| description | Abstract This paper comprehensively investigates the current distribution behaviours of paralleled SiC MOSFET devices under the parasitic coupling between gate and power loops. Three types of connection that are commonly adopted in actual applications, comprising common source connection (CSC), Kelvin source connection (KSC) and hybrid source connection (HSC), are thoroughly discussed. The influence mechanism of mismatch in values for three parasitic inductances on current sharing during different switching periods is studied in theory. Simulations and experiments are also carried out and results are used to validate the theoretical analysis. Parasitic capacitance, common source and quasi common source parasitic inductance couplings are the three main coupling modes between gate loop and power loop in a circuit with paralleled SiC MOSFETs. The current imbalance is mainly due to the variation of gate‐source voltage generated by the mismatch in the parasitic inductances through the three coupling paths. This paper aims to provide an insight into current sharing mechanism of paralleled devices with circuit parasitic mismatches. Influence of every parasitic inductance under each of the three coupling modes is investigated and recommendation made on choice of coupling mode and viable switching speed and current balance tradeoff that can be adopted in a practical system design. |
| first_indexed | 2024-12-10T08:29:50Z |
| format | Article |
| id | doaj.art-164be89d04f144ec9df7a212f9bb74e7 |
| institution | Directory Open Access Journal |
| issn | 1755-4535 1755-4543 |
| language | English |
| last_indexed | 2024-12-10T08:29:50Z |
| publishDate | 2022-08-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Power Electronics |
| spelling | doaj.art-164be89d04f144ec9df7a212f9bb74e72022-12-22T01:56:07ZengWileyIET Power Electronics1755-45351755-45432022-08-0115111075109210.1049/pel2.12292Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devicesHaoran Zhang0Junji Ke1Jiaoyang Peng2Peng Sun3Zhibin Zhao4State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources North China Electric Power University Changping District Beijing ChinaPower Semiconductor Business Unit Shanghai Belling Co., Ltd. Shanghai ChinaState Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources North China Electric Power University Changping District Beijing ChinaState Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources North China Electric Power University Changping District Beijing ChinaState Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources North China Electric Power University Changping District Beijing ChinaAbstract This paper comprehensively investigates the current distribution behaviours of paralleled SiC MOSFET devices under the parasitic coupling between gate and power loops. Three types of connection that are commonly adopted in actual applications, comprising common source connection (CSC), Kelvin source connection (KSC) and hybrid source connection (HSC), are thoroughly discussed. The influence mechanism of mismatch in values for three parasitic inductances on current sharing during different switching periods is studied in theory. Simulations and experiments are also carried out and results are used to validate the theoretical analysis. Parasitic capacitance, common source and quasi common source parasitic inductance couplings are the three main coupling modes between gate loop and power loop in a circuit with paralleled SiC MOSFETs. The current imbalance is mainly due to the variation of gate‐source voltage generated by the mismatch in the parasitic inductances through the three coupling paths. This paper aims to provide an insight into current sharing mechanism of paralleled devices with circuit parasitic mismatches. Influence of every parasitic inductance under each of the three coupling modes is investigated and recommendation made on choice of coupling mode and viable switching speed and current balance tradeoff that can be adopted in a practical system design.https://doi.org/10.1049/pel2.12292 |
| spellingShingle | Haoran Zhang Junji Ke Jiaoyang Peng Peng Sun Zhibin Zhao Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices IET Power Electronics |
| title | Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices |
| title_full | Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices |
| title_fullStr | Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices |
| title_full_unstemmed | Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices |
| title_short | Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices |
| title_sort | influence of parasitic coupling on current sharing in paralleled sic mosfet devices |
| url | https://doi.org/10.1049/pel2.12292 |
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