Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders
This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design. CNTFET and GNRFET-based ternary half adder (THA) and multiplier (TMUL) circuits has been designed using ternary unary operator circuits at 3...
Main Authors: | , , , , , , |
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Format: | Article |
Language: | English |
Published: |
EDP Sciences
2023-01-01
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Series: | E3S Web of Conferences |
Subjects: | |
Online Access: | https://www.e3s-conferences.org/articles/e3sconf/pdf/2023/28/e3sconf_icmed-icmpc2023_01220.pdf |