An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the P...

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Bibliographic Details
Main Authors: Javad Tavakoli, Hossein Miri Lavasani, Samad Sheikhaei
Format: Article
Language:English
Published: MDPI AG 2023-12-01
Series:Journal of Low Power Electronics and Applications
Subjects:
phase-locked loop
PLL
phase detector
PD
sampling PD
INPLL
Online Access:https://www.mdpi.com/2079-9268/13/4/65

Internet

https://www.mdpi.com/2079-9268/13/4/65

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