The Prism Bridge: Maximizing Inter-Chip AXI Throughput in the High-Speed Serial Era

The Prism Bridge: Maximizing Inter-Chip AXI Throughput in the High-Speed Serial Era

In this paper, we present the Prism Bridge, a soft IP core developed to bridge FPGA-MPSoC systems using high-speed serial links. Considering the current trend of ubiquitous serial transceivers with staggeringly increasing line rates, minimizing overhead and maximizing data throughput becomes paramou...

Full description

Bibliographic Details
Main Authors: Robert Drehmel, Hans-Ulrich Heiss
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
Cluster computing
computer architecture
field-programmable gate arrays
high-speed serial
inter-chip axi communication
protocols
Online Access:https://ieeexplore.ieee.org/document/10129908/

Internet

https://ieeexplore.ieee.org/document/10129908/

Similar Items