A 13-Bit 1-MS/s SAR ADC With Completion-Aware Background Capacitor Mismatch Calibration

A 13-Bit 1-MS/s SAR ADC With Completion-Aware Background Capacitor Mismatch Calibration

This paper introduces a completion-aware background sequential capacitor mismatch calibration technique for SAR ADC. The proposed method sequentially corrects capacitor mismatch from the lower to the upper bits in the CDAC. This calibration method can automatically detect when calibration is complet...

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Bibliographic Details
Main Authors: Sunghyun Bae, Sewon Lee, Siheon Seong, Sunwoo Kong, Bonghyuk Park, Minjae Lee
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
Analog-to-digital converter (ADC)
successive approximation register (SAR)
capacitor mismatch
background calibration
Online Access:https://ieeexplore.ieee.org/document/10258263/

Internet

https://ieeexplore.ieee.org/document/10258263/

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