Adaptive Linear Address Map for Bank Interleaving in DRAMs

Adaptive Linear Address Map for Bank Interleaving in DRAMs

The conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve memory system performance, the adaptive bank-interleaved linear address map for a DRAM technology is proposed. In our approach, the addresses are efficiently rea...

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Bibliographic Details
Main Authors: Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Address mapping
DRAM
embedded system
architecture
performance
Online Access:https://ieeexplore.ieee.org/document/8832137/

Internet

https://ieeexplore.ieee.org/document/8832137/

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