Adaptive Linear Address Map for Bank Interleaving in DRAMs
The conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve memory system performance, the adaptive bank-interleaved linear address map for a DRAM technology is proposed. In our approach, the addresses are efficiently rea...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8832137/ |
| _version_ | 1831526010209697792 |
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| author | Jae Young Hur Sang Woo Rhim Beom Hak Lee Wooyoung Jang |
| author_facet | Jae Young Hur Sang Woo Rhim Beom Hak Lee Wooyoung Jang |
| author_sort | Jae Young Hur |
| collection | DOAJ |
| description | The conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve memory system performance, the adaptive bank-interleaved linear address map for a DRAM technology is proposed. In our approach, the addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost. |
| first_indexed | 2024-12-16T16:01:33Z |
| format | Article |
| id | doaj.art-1ad9413b8fe247dc9674fdd53c215798 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-16T16:01:33Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-1ad9413b8fe247dc9674fdd53c2157982022-12-21T22:25:28ZengIEEEIEEE Access2169-35362019-01-01712960412961610.1109/ACCESS.2019.29403518832137Adaptive Linear Address Map for Bank Interleaving in DRAMsJae Young Hur0https://orcid.org/0000-0003-4151-908XSang Woo Rhim1Beom Hak Lee2Wooyoung Jang3https://orcid.org/0000-0002-7262-0028Faculty of Engineering, Vietnamese-German University, Ho Chi Minh, VietnamFaculty of Engineering, Vietnamese-German University, Ho Chi Minh, VietnamFaculty of Engineering, Vietnamese-German University, Ho Chi Minh, VietnamDepartment of Electronics and Electrical Engineering, Dankook University, Yongin, South KoreaThe conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve memory system performance, the adaptive bank-interleaved linear address map for a DRAM technology is proposed. In our approach, the addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost.https://ieeexplore.ieee.org/document/8832137/Address mappingDRAMembedded systemarchitectureperformance |
| spellingShingle | Jae Young Hur Sang Woo Rhim Beom Hak Lee Wooyoung Jang Adaptive Linear Address Map for Bank Interleaving in DRAMs IEEE Access Address mapping DRAM embedded system architecture performance |
| title | Adaptive Linear Address Map for Bank Interleaving in DRAMs |
| title_full | Adaptive Linear Address Map for Bank Interleaving in DRAMs |
| title_fullStr | Adaptive Linear Address Map for Bank Interleaving in DRAMs |
| title_full_unstemmed | Adaptive Linear Address Map for Bank Interleaving in DRAMs |
| title_short | Adaptive Linear Address Map for Bank Interleaving in DRAMs |
| title_sort | adaptive linear address map for bank interleaving in drams |
| topic | Address mapping DRAM embedded system architecture performance |
| url | https://ieeexplore.ieee.org/document/8832137/ |
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