Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide
We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO2/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented mod...
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| Format: | Article |
| Language: | English |
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AIMS Press
2022-03-01
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| Series: | AIMS Electronics and Electrical Engineering |
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| Online Access: | https://www.aimspress.com/article/doi/10.3934/electreng.2022007?viewType=HTML |