Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide
We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO2/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented mod...
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
AIMS Press
2022-03-01
|
| Series: | AIMS Electronics and Electrical Engineering |
| Subjects: | |
| Online Access: | https://www.aimspress.com/article/doi/10.3934/electreng.2022007?viewType=HTML |
| _version_ | 1811218139945369600 |
|---|---|
| author | Hakkee Jung |
| author_facet | Hakkee Jung |
| author_sort | Hakkee Jung |
| collection | DOAJ |
| description | We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO2/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-k dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-k dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-k dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-k dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO2/ZrO2, La2O3, and TiO2 with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL. |
| first_indexed | 2024-04-12T07:04:26Z |
| format | Article |
| id | doaj.art-1bd07889758940f7abd3237a9d4c9e68 |
| institution | Directory Open Access Journal |
| issn | 2578-1588 |
| language | English |
| last_indexed | 2024-04-12T07:04:26Z |
| publishDate | 2022-03-01 |
| publisher | AIMS Press |
| record_format | Article |
| series | AIMS Electronics and Electrical Engineering |
| spelling | doaj.art-1bd07889758940f7abd3237a9d4c9e682022-12-22T03:42:51ZengAIMS PressAIMS Electronics and Electrical Engineering2578-15882022-03-016210812310.3934/electreng.2022007Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxideHakkee Jung0Department of Electronic Eng., Kunsan National University, Gunsan-si, Jeollabuk-do, 54150, Republic of KoreaWe proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO2/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-k dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-k dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-k dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-k dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO2/ZrO2, La2O3, and TiO2 with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.https://www.aimspress.com/article/doi/10.3934/electreng.2022007?viewType=HTMLcylindrical surrounding gatejunctionlessthreshold voltagediblstacked oxidehigh-k |
| spellingShingle | Hakkee Jung Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide AIMS Electronics and Electrical Engineering cylindrical surrounding gate junctionless threshold voltage dibl stacked oxide high-k |
| title | Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide |
| title_full | Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide |
| title_fullStr | Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide |
| title_full_unstemmed | Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide |
| title_short | Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide |
| title_sort | analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate jlcsg mosfet using stacked high k oxide |
| topic | cylindrical surrounding gate junctionless threshold voltage dibl stacked oxide high-k |
| url | https://www.aimspress.com/article/doi/10.3934/electreng.2022007?viewType=HTML |
| work_keys_str_mv | AT hakkeejung analyticalmodelsofthresholdvoltageanddraininducedbarrierloweringinjunctionlesscylindricalsurroundinggatejlcsgmosfetusingstackedhighkoxide |