A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process

In this paper, a 180-nm CMOS ring oscillator design, made with halo-implanted transistors and operating in the weak inversion region, is proposed, based on an undergraduate integrated circuit design course methodology for building logic gates and comparing simulated results with reviewed literature...

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Main Authors: Vinícius Henrique Geraldo Correa, Rodrigo Aparecido da Silva Braga, Dean Bicudo Karolak, Fernanda Rodrigues Silva
Format: Article
Language:English
Published: ITB Journal Publisher 2023-08-01
Series:Journal of ICT Research and Applications
Subjects:
Online Access:https://journals.itb.ac.id/index.php/jictra/article/view/16725
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author Vinícius Henrique Geraldo Correa
Rodrigo Aparecido da Silva Braga
Dean Bicudo Karolak
Fernanda Rodrigues Silva
author_facet Vinícius Henrique Geraldo Correa
Rodrigo Aparecido da Silva Braga
Dean Bicudo Karolak
Fernanda Rodrigues Silva
author_sort Vinícius Henrique Geraldo Correa
collection DOAJ
description In this paper, a 180-nm CMOS ring oscillator design, made with halo-implanted transistors and operating in the weak inversion region, is proposed, based on an undergraduate integrated circuit design course methodology for building logic gates and comparing simulated results with reviewed literature data. Halo-implanted channel transistors have a steeper and less distorted voltage characteristic curve compared to uniformly doped channel ones, which makes them a more appropriate option when designing asynchronous digital integrated circuits aimed at low bias and low power. Three gate models were created using weak inversion and pull-up and pull-down networks made with halo-implanted transistors. The results of the study and simulation of the three inverter digital gate topologies showed that the NOT inverter model, as expected, had a higher frequency than the NAND and NOR inverter models. The ring oscillators made with the NOT inverter came up with an 8.25-MHz switching frequency as well as a dynamic power close to 270 nW. A comparison with other ring oscillators from previous studies is also shown.
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spelling doaj.art-1c14cf141e5b465186760fd791795d0f2023-09-01T08:00:18ZengITB Journal PublisherJournal of ICT Research and Applications2337-57872338-54992023-08-0117210.5614/itbj.ict.res.appl.2023.17.2.1A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm ProcessVinícius Henrique Geraldo Correa0Rodrigo Aparecido da Silva Braga1Dean Bicudo Karolak2Fernanda Rodrigues Silva3Institute of Sciences and Technology, Federal University of Itajuba – Campus Itabira, Itabira-MG, 35903087, BrazilInstitute of Sciences and Technology, Federal University of Itajuba – Campus Itabira, Itabira-MG, 35903087, BrazilInstitute of Sciences and Technology, Federal University of Itajuba – Campus Itabira, Itabira-MG, 35903087, BrazilInstitute of Sciences and Technology, Federal University of Itajuba – Campus Itabira, Itabira-MG, 35903087, Brazil In this paper, a 180-nm CMOS ring oscillator design, made with halo-implanted transistors and operating in the weak inversion region, is proposed, based on an undergraduate integrated circuit design course methodology for building logic gates and comparing simulated results with reviewed literature data. Halo-implanted channel transistors have a steeper and less distorted voltage characteristic curve compared to uniformly doped channel ones, which makes them a more appropriate option when designing asynchronous digital integrated circuits aimed at low bias and low power. Three gate models were created using weak inversion and pull-up and pull-down networks made with halo-implanted transistors. The results of the study and simulation of the three inverter digital gate topologies showed that the NOT inverter model, as expected, had a higher frequency than the NAND and NOR inverter models. The ring oscillators made with the NOT inverter came up with an 8.25-MHz switching frequency as well as a dynamic power close to 270 nW. A comparison with other ring oscillators from previous studies is also shown. https://journals.itb.ac.id/index.php/jictra/article/view/16725CMOShalo-implanted channelslow power integrated circuitsring oscillatorsweak inversion operation
spellingShingle Vinícius Henrique Geraldo Correa
Rodrigo Aparecido da Silva Braga
Dean Bicudo Karolak
Fernanda Rodrigues Silva
A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process
Journal of ICT Research and Applications
CMOS
halo-implanted channels
low power integrated circuits
ring oscillators
weak inversion operation
title A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process
title_full A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process
title_fullStr A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process
title_full_unstemmed A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process
title_short A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process
title_sort subthreshold biased cmos ring oscillator model design in 180 nm process
topic CMOS
halo-implanted channels
low power integrated circuits
ring oscillators
weak inversion operation
url https://journals.itb.ac.id/index.php/jictra/article/view/16725
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