The effect of annealing temperature on the characterization and electrical characteristics of NiO/PVC gate dielectric
The thickness of silicon oxide gate dielectric for field effect transistors is 1 to 2 nm. Therefore, reducing the thickness of gate to 1 nm for future products will increase the tunelling and leakage currents. The hybrid nano composites are good candidates as dielectric gates with high dielectric co...
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| Format: | Article |
| Language: | English |
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Isfahan University of Technology
2021-08-01
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| Series: | Iranian Journal of Physics Research |
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| Online Access: | http://ijpr.iut.ac.ir/article_1708_7432a5334c6c7b161d1af7882d5838a3.pdf |