A BIST Scheme for Bootstrapped Switches
This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS tran...
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MDPI AG
2021-07-01
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Series: | Electronics |
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Online Access: | https://www.mdpi.com/2079-9292/10/14/1661 |
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author | Xiao-Bin Tang Masayoshi Tachibana |
author_facet | Xiao-Bin Tang Masayoshi Tachibana |
author_sort | Xiao-Bin Tang |
collection | DOAJ |
description | This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS transistor is greater than or equal to the supply voltage when the switch is turn on, and such a voltage is not suitable for observation. To solve this problem, a low power supply voltage is provided for the bootstrapped switch to obtain a suitable observation voltage. The proposed BIST scheme and the circuit under test (CUT) are realized with transistor level. The proposed BIST scheme was simulated by HSPICE. The simulated fault coverage is approximately 87.9% with 66 test circuits. |
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format | Article |
id | doaj.art-1d2089a63cc54d9e9becff612346c7a3 |
institution | Directory Open Access Journal |
issn | 2079-9292 |
language | English |
last_indexed | 2024-03-10T09:40:51Z |
publishDate | 2021-07-01 |
publisher | MDPI AG |
record_format | Article |
series | Electronics |
spelling | doaj.art-1d2089a63cc54d9e9becff612346c7a32023-11-22T03:38:03ZengMDPI AGElectronics2079-92922021-07-011014166110.3390/electronics10141661A BIST Scheme for Bootstrapped SwitchesXiao-Bin Tang0Masayoshi Tachibana1Electronic and Photonic Systems Engineering, Kochi University of Technology, Kami, Kochi 782-8502, JapanElectronic and Photonic Systems Engineering, Kochi University of Technology, Kami, Kochi 782-8502, JapanThis paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS transistor is greater than or equal to the supply voltage when the switch is turn on, and such a voltage is not suitable for observation. To solve this problem, a low power supply voltage is provided for the bootstrapped switch to obtain a suitable observation voltage. The proposed BIST scheme and the circuit under test (CUT) are realized with transistor level. The proposed BIST scheme was simulated by HSPICE. The simulated fault coverage is approximately 87.9% with 66 test circuits.https://www.mdpi.com/2079-9292/10/14/1661built-in self-testfault diagnosisbootstrapped switches |
spellingShingle | Xiao-Bin Tang Masayoshi Tachibana A BIST Scheme for Bootstrapped Switches Electronics built-in self-test fault diagnosis bootstrapped switches |
title | A BIST Scheme for Bootstrapped Switches |
title_full | A BIST Scheme for Bootstrapped Switches |
title_fullStr | A BIST Scheme for Bootstrapped Switches |
title_full_unstemmed | A BIST Scheme for Bootstrapped Switches |
title_short | A BIST Scheme for Bootstrapped Switches |
title_sort | bist scheme for bootstrapped switches |
topic | built-in self-test fault diagnosis bootstrapped switches |
url | https://www.mdpi.com/2079-9292/10/14/1661 |
work_keys_str_mv | AT xiaobintang abistschemeforbootstrappedswitches AT masayoshitachibana abistschemeforbootstrappedswitches AT xiaobintang bistschemeforbootstrappedswitches AT masayoshitachibana bistschemeforbootstrappedswitches |