Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment
Timing closure remains one of the most critical challenges of a physical synthesis flow, especially when the design operates under multiple operating conditions. Even if timing is almost closed at the end of the flow, last-mile placement and routing congestion optimizations may introduce new timing...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-11-01
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| Series: | Technologies |
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| Online Access: | https://www.mdpi.com/2227-7080/9/4/92 |
| _version_ | 1797500215548182528 |
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| author | Dimitrios Mangiras Giorgos Dimitrakopoulos |
| author_facet | Dimitrios Mangiras Giorgos Dimitrakopoulos |
| author_sort | Dimitrios Mangiras |
| collection | DOAJ |
| description | Timing closure remains one of the most critical challenges of a physical synthesis flow, especially when the design operates under multiple operating conditions. Even if timing is almost closed at the end of the flow, last-mile placement and routing congestion optimizations may introduce new timing violations. Correcting such violations needs minimally disruptive techniques such as threshold voltage reassignment and gate sizing that affect only marginally the placement and routing of the almost finalized design. To this end, we transform a powerful Lagrangian-relaxation-based optimizer, used for global timing optimization early in the design flow, into a practical incremental timing optimizer that corrects small timing violations with fast runtime and without increasing the area/power of the design. The proposed approach was applied to already optimized designs of the ISPD 2013 benchmarks assuming that they experience new timing violations due to local wire rerouting. Experimental results show that in single corner designs, timing is improved by more than 36% on average, using 45% less runtime. Correspondingly, in a multicorner context, timing is improved by 39% when compared to the fully-fledged version of the timing optimizer. |
| first_indexed | 2024-03-10T03:58:42Z |
| format | Article |
| id | doaj.art-1d7c22247d224bc5b7e2a44a6423db01 |
| institution | Directory Open Access Journal |
| issn | 2227-7080 |
| language | English |
| last_indexed | 2024-03-10T03:58:42Z |
| publishDate | 2021-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Technologies |
| spelling | doaj.art-1d7c22247d224bc5b7e2a44a6423db012023-11-23T10:48:16ZengMDPI AGTechnologies2227-70802021-11-01949210.3390/technologies9040092Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage AssignmentDimitrios Mangiras0Giorgos Dimitrakopoulos1Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi, GreeceElectrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi, GreeceTiming closure remains one of the most critical challenges of a physical synthesis flow, especially when the design operates under multiple operating conditions. Even if timing is almost closed at the end of the flow, last-mile placement and routing congestion optimizations may introduce new timing violations. Correcting such violations needs minimally disruptive techniques such as threshold voltage reassignment and gate sizing that affect only marginally the placement and routing of the almost finalized design. To this end, we transform a powerful Lagrangian-relaxation-based optimizer, used for global timing optimization early in the design flow, into a practical incremental timing optimizer that corrects small timing violations with fast runtime and without increasing the area/power of the design. The proposed approach was applied to already optimized designs of the ISPD 2013 benchmarks assuming that they experience new timing violations due to local wire rerouting. Experimental results show that in single corner designs, timing is improved by more than 36% on average, using 45% less runtime. Correspondingly, in a multicorner context, timing is improved by 39% when compared to the fully-fledged version of the timing optimizer.https://www.mdpi.com/2227-7080/9/4/92incremental power and timing optimizationLagrangian relaxationgate sizingmultimode multicornerphysical optimization |
| spellingShingle | Dimitrios Mangiras Giorgos Dimitrakopoulos Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment Technologies incremental power and timing optimization Lagrangian relaxation gate sizing multimode multicorner physical optimization |
| title | Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment |
| title_full | Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment |
| title_fullStr | Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment |
| title_full_unstemmed | Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment |
| title_short | Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment |
| title_sort | incremental lagrangian relaxation based discrete gate sizing and threshold voltage assignment |
| topic | incremental power and timing optimization Lagrangian relaxation gate sizing multimode multicorner physical optimization |
| url | https://www.mdpi.com/2227-7080/9/4/92 |
| work_keys_str_mv | AT dimitriosmangiras incrementallagrangianrelaxationbaseddiscretegatesizingandthresholdvoltageassignment AT giorgosdimitrakopoulos incrementallagrangianrelaxationbaseddiscretegatesizingandthresholdvoltageassignment |