Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization
In this paper, we propose a model-based workflow to generate parallel code on a multiple instruction stream, multiple data stream (MIMD) processor with vector accelerator (MIMDV) from a Simulink model. Solving data- and task-parallelism is crucial during this process. For data parallelism, a RISC-V...
| 主要な著者: | , , , |
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| フォーマット: | 論文 |
| 言語: | English |
| 出版事項: |
IEEE
2024-01-01
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| シリーズ: | IEEE Access |
| 主題: | |
| オンライン･アクセス: | https://ieeexplore.ieee.org/document/10460525/ |