An IP Core of AMBA Bus Interface in HDL
The AMBA on-chip bus architecture is a well-known open specification that explains how to connect and manage the functional units that make up a System-On-Chip (SoC). The design and implementation of an AHB Master, RAM, ROM, FIFO and Memory Controller implementation is proposed in this paper. It is...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2022-01-01
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| Series: | ITM Web of Conferences |
| Online Access: | https://www.itm-conferences.org/articles/itmconf/pdf/2022/10/itmconf_icaect2022_02004.pdf |