Performance Enhancement Counter with Minimal Clock Period
A synchronous binary counter is a fundamental component in VLSI design which are used commonly. synchronous binary counter is fast and are used in many applications as it supports wide bit-width. Due to large fan-outs and long carry chains many previous counters have low counting rate when the size...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2023-01-01
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| Series: | E3S Web of Conferences |
| Online Access: | https://www.e3s-conferences.org/articles/e3sconf/pdf/2023/36/e3sconf_iconnect2023_01005.pdf |