Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

Invertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic ha...

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Bibliographic Details
Main Authors: Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Open Journal of Circuits and Systems
Subjects:
Boltzmann machine
sparse matrix
FPGA
integer factorization
Online Access:https://ieeexplore.ieee.org/document/9645044/

Internet

https://ieeexplore.ieee.org/document/9645044/

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