Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices
Invertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic ha...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/9645044/ |
| _version_ | 1819364482580742144 |
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| author | Naoya Onizawa Akira Tamakoshi Takahiro Hanyu |
| author_facet | Naoya Onizawa Akira Tamakoshi Takahiro Hanyu |
| author_sort | Naoya Onizawa |
| collection | DOAJ |
| description | Invertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic has not been studied. In this paper, we introduce a scalable hardware architecture based on sparse Hamiltonian matrices. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, PTELL achieves around 1% and 10% memory usages of a conventional dense and ELL matrices, respectively, in case of invertible multipliers. In addition, the proposed hardware accelerator of invertible logic for supporting arbitrary Hamiltonians is implemented on Xilinx VU9P FPGA, which achieves around two orders of magnitude faster than a 16-core Intel Xeon implementation. |
| first_indexed | 2024-12-24T22:59:39Z |
| format | Article |
| id | doaj.art-20826c96c8834c70930036fcdf2f8f58 |
| institution | Directory Open Access Journal |
| issn | 2644-1225 |
| language | English |
| last_indexed | 2024-12-24T22:59:39Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj.art-20826c96c8834c70930036fcdf2f8f582022-12-21T16:35:10ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252021-01-01278279110.1109/OJCAS.2021.31165849645044Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian MatricesNaoya Onizawa0https://orcid.org/0000-0002-4855-7081Akira Tamakoshi1https://orcid.org/0000-0002-7348-8196Takahiro Hanyu2Research Institute of Electrical Communication, Tohoku University, Sendai, JapanResearch Institute of Electrical Communication, Tohoku University, Sendai, JapanResearch Institute of Electrical Communication, Tohoku University, Sendai, JapanInvertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic has not been studied. In this paper, we introduce a scalable hardware architecture based on sparse Hamiltonian matrices. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, PTELL achieves around 1% and 10% memory usages of a conventional dense and ELL matrices, respectively, in case of invertible multipliers. In addition, the proposed hardware accelerator of invertible logic for supporting arbitrary Hamiltonians is implemented on Xilinx VU9P FPGA, which achieves around two orders of magnitude faster than a 16-core Intel Xeon implementation.https://ieeexplore.ieee.org/document/9645044/Boltzmann machinesparse matrixFPGAinteger factorization |
| spellingShingle | Naoya Onizawa Akira Tamakoshi Takahiro Hanyu Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices IEEE Open Journal of Circuits and Systems Boltzmann machine sparse matrix FPGA integer factorization |
| title | Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices |
| title_full | Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices |
| title_fullStr | Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices |
| title_full_unstemmed | Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices |
| title_short | Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices |
| title_sort | hardware acceleration of large scale cmos invertible logic based on sparse hamiltonian matrices |
| topic | Boltzmann machine sparse matrix FPGA integer factorization |
| url | https://ieeexplore.ieee.org/document/9645044/ |
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