Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set Extension

Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set Extension

Random linear network coding (RLNC) can greatly aid data transmission in lossy wireless networks. However, RLNC requires computationally complex matrix multiplications and inversions in finite fields (Galois fields). These computations are highly demanding for energy-constrained mobile devices. The...

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Bibliographic Details
Main Authors: Javier Acevedo, Robert Scheffel, Simon Wunderlich, Mattis Hasler, Sreekrishna Pandi, Juan Cabrera, Frank H. P. Fitzek, Gerhard Fettweis, Martin Reisslein
Format: Article
Language:English
Published: MDPI AG 2018-09-01
Series:Electronics
Subjects:
application-specific instruction-set processor (ASIP)
flexible-length instruction extension (FLIX)
galois field
hardware acceleration
multiply-accumulate (MAC) operations
random linear network coding (RLNC)
single instruction multiple data (SIMD)
Online Access:http://www.mdpi.com/2079-9292/7/9/180

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http://www.mdpi.com/2079-9292/7/9/180

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