A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Registe...

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Bibliographic Details
Main Authors: Deeksha Verma, Behnam S. Rikan, Khuram Shehzad, Sung Jin Kim, Danial Khan, Venkatesh Kommangunta, Syed Adil Ali Shah, Younggun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Adaptive power control (APC)
comparator offset calibration
hybrid type time interleaved SAR ADC
low power consumption
redundant capacitor
time-skew calibration
Online Access:https://ieeexplore.ieee.org/document/9548087/

Internet

https://ieeexplore.ieee.org/document/9548087/

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