| Summary: | We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (T<sub>sub</sub>) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ V<sub>th</sub> ± 0.8 V, and higher I<sub>on</sub>/I<sub>off</sub> (>10<sup>5</sup> @|V<sub>d</sub>| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to V<sub>th</sub> roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.
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