Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits
We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep...
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2020-07-01
|
| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/11/8/741 |
| _version_ | 1797560834103181312 |
|---|---|
| author | Tung-Ying Hsieh Ping-Yi Hsieh Chih-Chao Yang Chang-Hong Shen Jia-Min Shieh Wen-Kuan Yeh Meng-Chyi Wu |
| author_facet | Tung-Ying Hsieh Ping-Yi Hsieh Chih-Chao Yang Chang-Hong Shen Jia-Min Shieh Wen-Kuan Yeh Meng-Chyi Wu |
| author_sort | Tung-Ying Hsieh |
| collection | DOAJ |
| description | We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (T<sub>sub</sub>) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ V<sub>th</sub> ± 0.8 V, and higher I<sub>on</sub>/I<sub>off</sub> (>10<sup>5</sup> @|V<sub>d</sub>| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to V<sub>th</sub> roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications. |
| first_indexed | 2024-03-10T18:05:51Z |
| format | Article |
| id | doaj.art-22a985f4cf5044729dee059c539d9738 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-10T18:05:51Z |
| publishDate | 2020-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-22a985f4cf5044729dee059c539d97382023-11-20T08:29:29ZengMDPI AGMicromachines2072-666X2020-07-0111874110.3390/mi11080741Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated CircuitsTung-Ying Hsieh0Ping-Yi Hsieh1Chih-Chao Yang2Chang-Hong Shen3Jia-Min Shieh4Wen-Kuan Yeh5Meng-Chyi Wu6Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, TaiwanTaiwan Semiconductor Research Institute, No.26, Prosperity Road 1, Hsinchu 30013, TaiwanTaiwan Semiconductor Research Institute, No.26, Prosperity Road 1, Hsinchu 30013, TaiwanTaiwan Semiconductor Research Institute, No.26, Prosperity Road 1, Hsinchu 30013, TaiwanTaiwan Semiconductor Research Institute, No.26, Prosperity Road 1, Hsinchu 30013, TaiwanTaiwan Semiconductor Research Institute, No.26, Prosperity Road 1, Hsinchu 30013, TaiwanInstitute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, TaiwanWe introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (T<sub>sub</sub>) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ V<sub>th</sub> ± 0.8 V, and higher I<sub>on</sub>/I<sub>off</sub> (>10<sup>5</sup> @|V<sub>d</sub>| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to V<sub>th</sub> roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.https://www.mdpi.com/2072-666X/11/8/741monolithic 3Dgate-all-aroundnanowire FETlow-thermal budgetlocation-controlled-grainlaser crystallization |
| spellingShingle | Tung-Ying Hsieh Ping-Yi Hsieh Chih-Chao Yang Chang-Hong Shen Jia-Min Shieh Wen-Kuan Yeh Meng-Chyi Wu Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits Micromachines monolithic 3D gate-all-around nanowire FET low-thermal budget location-controlled-grain laser crystallization |
| title | Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits |
| title_full | Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits |
| title_fullStr | Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits |
| title_full_unstemmed | Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits |
| title_short | Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits |
| title_sort | single grain gate all around si nanowire fet using low thermal budget processes for monolithic three dimensional integrated circuits |
| topic | monolithic 3D gate-all-around nanowire FET low-thermal budget location-controlled-grain laser crystallization |
| url | https://www.mdpi.com/2072-666X/11/8/741 |
| work_keys_str_mv | AT tungyinghsieh singlegraingateallaroundsinanowirefetusinglowthermalbudgetprocessesformonolithicthreedimensionalintegratedcircuits AT pingyihsieh singlegraingateallaroundsinanowirefetusinglowthermalbudgetprocessesformonolithicthreedimensionalintegratedcircuits AT chihchaoyang singlegraingateallaroundsinanowirefetusinglowthermalbudgetprocessesformonolithicthreedimensionalintegratedcircuits AT changhongshen singlegraingateallaroundsinanowirefetusinglowthermalbudgetprocessesformonolithicthreedimensionalintegratedcircuits AT jiaminshieh singlegraingateallaroundsinanowirefetusinglowthermalbudgetprocessesformonolithicthreedimensionalintegratedcircuits AT wenkuanyeh singlegraingateallaroundsinanowirefetusinglowthermalbudgetprocessesformonolithicthreedimensionalintegratedcircuits AT mengchyiwu singlegraingateallaroundsinanowirefetusinglowthermalbudgetprocessesformonolithicthreedimensionalintegratedcircuits |