Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In JL mode, the ON current (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {ON}}$ </tex-math...

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Bibliographic Details
Main Authors: V. Bharath Sreenivasulu, Aruna Kumari Neelam, Sekhar Reddy Kola, Jawar Singh, Yiming Li
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
CMOS inverter
CS amplifier
inversion
junctionless
nanosheet FET
Verilog-A
Online Access:https://ieeexplore.ieee.org/document/10223227/

Internet

https://ieeexplore.ieee.org/document/10223227/

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