| Summary: | In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In JL mode, the ON current (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {ON}}$ </tex-math></inline-formula>) rises with an increase in temperature compared to the downfall trend in INV mode. In addition, compared to JL mode, the INV mode exhibits a better negative temperature coefficient of threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{d}V_{\mathrm {th}}$ </tex-math></inline-formula>/dT). Further, the mixed mode circuit simulations are carried out using the Cadence Virtuoso platform through the Verilog-A model. From the analysis, it is observed that an increase of 20% gain in INV mode compared to JL mode for a common source (CS) amplifier. The JL mode NS-FETs achieve higher CMOS inverter switching current (<inline-formula> <tex-math notation="LaTeX">$I_{SC}$ </tex-math></inline-formula>) and lower energy-delay products (EDP) as temperature rises. A three-stage ring oscillator (RO) is designed, and the oscillation frequencies (<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm {OSC}}$ </tex-math></inline-formula>) of 43.39 GHz and 38.8 GHz are obtained with INV and JL modes. Although JL NS-FET offers less intrinsic capacitances, the <inline-formula> <tex-math notation="LaTeX">$f_{\mathrm {OSC}}$ </tex-math></inline-formula> is high for INV mode due to higher <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {ON}}$ </tex-math></inline-formula>. Furthermore, reducing supply voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula>), the <inline-formula> <tex-math notation="LaTeX">$f_{\mathrm {OSC}}$ </tex-math></inline-formula> falls by 67% with INV and 62.6% with JL modes. These results will give a better understanding of this emerging NS-FET at both device and circuit levels at advanced technology nodes.
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