An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multi...

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Bibliographic Details
Main Authors: Hsuan-Lun Kuo, Chih-Wen Lu, Poki Chen
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
SAR ADC
non-binary-weighted CDAC
multiple-LSB redundant CDAC
Online Access:https://ieeexplore.ieee.org/document/9312602/

Internet

https://ieeexplore.ieee.org/document/9312602/

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