An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC
A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multi...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9312602/ |
| _version_ | 1818351160967299072 |
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| author | Hsuan-Lun Kuo Chih-Wen Lu Poki Chen |
| author_facet | Hsuan-Lun Kuo Chih-Wen Lu Poki Chen |
| author_sort | Hsuan-Lun Kuo |
| collection | DOAJ |
| description | A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18-μm 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as -0.4/0.54 and -0.81/0.89 LSB, respectively, where 1 LSB = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s. |
| first_indexed | 2024-12-13T18:33:20Z |
| format | Article |
| id | doaj.art-24b8504add1d4cc4b90098043781a7ff |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-13T18:33:20Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-24b8504add1d4cc4b90098043781a7ff2022-12-21T23:35:25ZengIEEEIEEE Access2169-35362021-01-0195651566910.1109/ACCESS.2020.30489799312602An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DACHsuan-Lun Kuo0https://orcid.org/0000-0002-0062-1013Chih-Wen Lu1https://orcid.org/0000-0002-8935-6745Poki Chen2https://orcid.org/0000-0003-0749-4181Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.CDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.CDepartment of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan, R.O.CA low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18-μm 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as -0.4/0.54 and -0.81/0.89 LSB, respectively, where 1 LSB = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.https://ieeexplore.ieee.org/document/9312602/SAR ADCnon-binary-weighted CDACmultiple-LSB redundant CDAC |
| spellingShingle | Hsuan-Lun Kuo Chih-Wen Lu Poki Chen An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC IEEE Access SAR ADC non-binary-weighted CDAC multiple-LSB redundant CDAC |
| title | An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC |
| title_full | An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC |
| title_fullStr | An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC |
| title_full_unstemmed | An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC |
| title_short | An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC |
| title_sort | 18 39 fj conversion step 1 ms s 12 bit sar adc with non binary multiple lsb redundant and non integer and split capacitor dac |
| topic | SAR ADC non-binary-weighted CDAC multiple-LSB redundant CDAC |
| url | https://ieeexplore.ieee.org/document/9312602/ |
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