Test Program Generation for Microprocessors Based on Pipeline Hazards Templates
In this work, a method for the automated test programs generation aimed at the verification of microprocessor control logic is considered. The method is based on formal specification of a microprocessor instruction set and description of pipeline hazards templates. The use of formal specifications a...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Ivannikov Institute for System Programming of the Russian Academy of Sciences
2018-10-01
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| Series: | Труды Института системного программирования РАН |
| Subjects: | |
| Online Access: | https://ispranproceedings.elpub.ru/jour/article/view/1080 |
| _version_ | 1818065182359814144 |
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| author | D. N. Vorobyev A. S. Kamkin |
| author_facet | D. N. Vorobyev A. S. Kamkin |
| author_sort | D. N. Vorobyev |
| collection | DOAJ |
| description | In this work, a method for the automated test programs generation aimed at the verification of microprocessor control logic is considered. The method is based on formal specification of a microprocessor instruction set and description of pipeline hazards templates. The use of formal specifications allows automating development of test program generators and systematically testing control logic. At the same time, since the approach utilizes high-level descriptions that do not take into account cycle-accurate functioning of a pipeline, all the specifications and templates developed, as well as the constructed test programs, can be reused when the microarchitecture is modified. It makes it possible to apply the method at early stages of the microprocessor design cycle when frequent design changes are possible. |
| first_indexed | 2024-12-10T14:47:49Z |
| format | Article |
| id | doaj.art-24c5594b039e4243a3ceebf75f6e809a |
| institution | Directory Open Access Journal |
| issn | 2079-8156 2220-6426 |
| language | English |
| last_indexed | 2024-12-10T14:47:49Z |
| publishDate | 2018-10-01 |
| publisher | Ivannikov Institute for System Programming of the Russian Academy of Sciences |
| record_format | Article |
| series | Труды Института системного программирования РАН |
| spelling | doaj.art-24c5594b039e4243a3ceebf75f6e809a2022-12-22T01:44:31ZengIvannikov Institute for System Programming of the Russian Academy of SciencesТруды Института системного программирования РАН2079-81562220-64262018-10-011801080Test Program Generation for Microprocessors Based on Pipeline Hazards TemplatesD. N. Vorobyev0A. S. Kamkin1ИСП РАНИСП РАНIn this work, a method for the automated test programs generation aimed at the verification of microprocessor control logic is considered. The method is based on formal specification of a microprocessor instruction set and description of pipeline hazards templates. The use of formal specifications allows automating development of test program generators and systematically testing control logic. At the same time, since the approach utilizes high-level descriptions that do not take into account cycle-accurate functioning of a pipeline, all the specifications and templates developed, as well as the constructed test programs, can be reused when the microarchitecture is modified. It makes it possible to apply the method at early stages of the microprocessor design cycle when frequent design changes are possible.https://ispranproceedings.elpub.ru/jour/article/view/1080<i>построение тестовых программ</i><i>верификации управляющей логики микропроцессоров</i><i>формальные спецификации</i> |
| spellingShingle | D. N. Vorobyev A. S. Kamkin Test Program Generation for Microprocessors Based on Pipeline Hazards Templates Труды Института системного программирования РАН <i>построение тестовых программ</i> <i>верификации управляющей логики микропроцессоров</i> <i>формальные спецификации</i> |
| title | Test Program Generation for Microprocessors Based on Pipeline Hazards Templates |
| title_full | Test Program Generation for Microprocessors Based on Pipeline Hazards Templates |
| title_fullStr | Test Program Generation for Microprocessors Based on Pipeline Hazards Templates |
| title_full_unstemmed | Test Program Generation for Microprocessors Based on Pipeline Hazards Templates |
| title_short | Test Program Generation for Microprocessors Based on Pipeline Hazards Templates |
| title_sort | test program generation for microprocessors based on pipeline hazards templates |
| topic | <i>построение тестовых программ</i> <i>верификации управляющей логики микропроцессоров</i> <i>формальные спецификации</i> |
| url | https://ispranproceedings.elpub.ru/jour/article/view/1080 |
| work_keys_str_mv | AT dnvorobyev testprogramgenerationformicroprocessorsbasedonpipelinehazardstemplates AT askamkin testprogramgenerationformicroprocessorsbasedonpipelinehazardstemplates |