Design of canonical signed digit multiplier using spurious power suppression technique adder

Design of canonical signed digit multiplier using spurious power suppression technique adder

Abstract Reducing power consumption is a major challenge in developing integrated processors for smart portable devices. This is particularly important for extending battery life and ensuring extended usage of the device. However, some DSP processing applications involve complex algorithms that cons...

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Bibliographic Details
Main Authors: Jayalakshmi K. P., Priya Seema Miranda, K. Aarya Shri
Format: Article
Language:English
Published: SpringerOpen 2023-07-01
Series:Journal of Engineering and Applied Science
Subjects:
SPST
CSD
FFT
Canonical signed digit
Most significant part
Low power
Online Access:https://doi.org/10.1186/s44147-023-00254-0

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