Design of a 16-by-16-bit Unsigned Serial-parallel Multiplier using Retime Technique
In this paper, the structure of a 16-by-16 unsigned hybrid (serial-parallel) multiplier has been proposed. Parallel multipliers, in comparison with serial multipliers, have higher speed and higher power consumption. In hybrid structures, to reduce power and increase speed, both serial and parallel t...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
OICC Press
2024-02-01
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| Series: | Majlesi Journal of Electrical Engineering |
| Subjects: | |
| Online Access: | https://oiccpress.com/mjee/article/view/4854 |