Low‐Power and Low‐Hardware Bit‐Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

Low‐Power and Low‐Hardware Bit‐Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In th...

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Bibliographic Details
Main Authors: Sudha Ellison Mathe, Lakshmi Boppana
Format: Article
Language:English
Published: Electronics and Telecommunications Research Institute (ETRI) 2017-08-01
Series:ETRI Journal
Subjects:
Finite field
Cryptography
Systolic
Polynomial basis
Application‐specific integrated circuit
Field programmable gate arrays
Online Access:https://doi.org/10.4218/etrij.17.0116.0770

Internet

https://doi.org/10.4218/etrij.17.0116.0770

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