Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10478888/ |
| _version_ | 1826865650335744000 |
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| author | Saion K. Roy Naresh R. Shanbhag |
| author_facet | Saion K. Roy Naresh R. Shanbhag |
| author_sort | Saion K. Roy |
| collection | DOAJ |
| description | Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters that affect it. We further analyze the fundamental limits on the SNDR of magnetoresistive random access memory (MRAM-), resistive random access memory (ReRAM-), and ferroelectric field effect transistor (FeFET)-based IMCs employing parameter variation and noise models that were validated against measured results from a recent MRAM-based IMC prototype in a 22 nm process. At high-output signal magnitude, we can find that the maximum achievable SNDR is limited by the pre-analog-to-digital-converter (ADC) array nonidealities, such as the conductance variations (CVs), parasitic resistances, and current mirror mismatch (MM), whereas the ADC thermal (AT) noise limits the SNDR at small signal magnitudes. Furthermore, for large dot-product (DP) dimensions (<inline-formula> <tex-math notation="LaTeX">$N > 50$ </tex-math></inline-formula>), the maximum achievable SNDR is highest for FeFET, followed by ReRAM and then MRAM. Finally, the increase in conductance contrast (<inline-formula> <tex-math notation="LaTeX">${g_ {\text {ON}} }/ {g_ {\text {OFF}} }$ </tex-math></inline-formula>) enhances the maximum achievable SNDR only until it reaches a value of approximately 12. ReRAMs and FeFETs demonstrate high energy efficiencies while achieving high SNDR, as their low conductance values lead to lower currents and lower noise due to wire parasitics. In all cases, across all three device types, DP dimension, ADC precision, and conductance contrast, the maximum achievable SNDR is found to be in the range of 18–22 dB, barely meeting the minimum needed for achieving an inference accuracy close to an equivalent fixed-point digital architecture. Finally, we demonstrate a network-level accuracy of 84.5% when mapping an ResNet-20 (CIFAR-10) by ReRAM-based architecture at a SNDR of 22 dB, in which MRAM- and FeFET-based architectures cannot realize. This result clearly implies the need for other approaches, e.g., algorithmic- and learning-based methods, to improve the inference accuracy of resistive IMC architectures. |
| first_indexed | 2024-04-24T11:00:28Z |
| format | Article |
| id | doaj.art-28107b97e2f8428e821dcc1d60abbe85 |
| institution | Directory Open Access Journal |
| issn | 2329-9231 |
| language | English |
| last_indexed | 2025-02-16T21:46:08Z |
| publishDate | 2024-01-01 |
| publisher | IEEE |
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| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj.art-28107b97e2f8428e821dcc1d60abbe852025-01-17T00:00:26ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-0110223010.1109/JXCDC.2024.338188810478888Energy-Accuracy Trade-Offs for Resistive In-Memory Computing ArchitecturesSaion K. Roy0https://orcid.org/0000-0001-7893-7168Naresh R. Shanbhag1https://orcid.org/0000-0002-4323-9164Department of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Urbana, IL, USADepartment of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Urbana, IL, USAResistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters that affect it. We further analyze the fundamental limits on the SNDR of magnetoresistive random access memory (MRAM-), resistive random access memory (ReRAM-), and ferroelectric field effect transistor (FeFET)-based IMCs employing parameter variation and noise models that were validated against measured results from a recent MRAM-based IMC prototype in a 22 nm process. At high-output signal magnitude, we can find that the maximum achievable SNDR is limited by the pre-analog-to-digital-converter (ADC) array nonidealities, such as the conductance variations (CVs), parasitic resistances, and current mirror mismatch (MM), whereas the ADC thermal (AT) noise limits the SNDR at small signal magnitudes. Furthermore, for large dot-product (DP) dimensions (<inline-formula> <tex-math notation="LaTeX">$N > 50$ </tex-math></inline-formula>), the maximum achievable SNDR is highest for FeFET, followed by ReRAM and then MRAM. Finally, the increase in conductance contrast (<inline-formula> <tex-math notation="LaTeX">${g_ {\text {ON}} }/ {g_ {\text {OFF}} }$ </tex-math></inline-formula>) enhances the maximum achievable SNDR only until it reaches a value of approximately 12. ReRAMs and FeFETs demonstrate high energy efficiencies while achieving high SNDR, as their low conductance values lead to lower currents and lower noise due to wire parasitics. In all cases, across all three device types, DP dimension, ADC precision, and conductance contrast, the maximum achievable SNDR is found to be in the range of 18–22 dB, barely meeting the minimum needed for achieving an inference accuracy close to an equivalent fixed-point digital architecture. Finally, we demonstrate a network-level accuracy of 84.5% when mapping an ResNet-20 (CIFAR-10) by ReRAM-based architecture at a SNDR of 22 dB, in which MRAM- and FeFET-based architectures cannot realize. This result clearly implies the need for other approaches, e.g., algorithmic- and learning-based methods, to improve the inference accuracy of resistive IMC architectures.https://ieeexplore.ieee.org/document/10478888/Embedded nonvolatile memory (eNVM)ferroelectric field effect transistor (FeFET)in-memory computing (IMC)magnetoresistive random access memory (MRAM)parallel barresistive random access memory (ReRAM) |
| spellingShingle | Saion K. Roy Naresh R. Shanbhag Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Embedded nonvolatile memory (eNVM) ferroelectric field effect transistor (FeFET) in-memory computing (IMC) magnetoresistive random access memory (MRAM) parallel bar resistive random access memory (ReRAM) |
| title | Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures |
| title_full | Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures |
| title_fullStr | Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures |
| title_full_unstemmed | Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures |
| title_short | Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures |
| title_sort | energy accuracy trade offs for resistive in memory computing architectures |
| topic | Embedded nonvolatile memory (eNVM) ferroelectric field effect transistor (FeFET) in-memory computing (IMC) magnetoresistive random access memory (MRAM) parallel bar resistive random access memory (ReRAM) |
| url | https://ieeexplore.ieee.org/document/10478888/ |
| work_keys_str_mv | AT saionkroy energyaccuracytradeoffsforresistiveinmemorycomputingarchitectures AT nareshrshanbhag energyaccuracytradeoffsforresistiveinmemorycomputingarchitectures |