Power Optimization For Multi-Core Memory Controller Using Intelligent Clock Gating Technique

Power Optimization For Multi-Core Memory Controller Using Intelligent Clock Gating Technique

The demand for low-power digital systems is increasing daily, especially for the multi-core design on SoC. Different IP cores of the existing multi-core memory controller need to communicate to achieve specific tasks on the same die. The system clock toggles each synchronous part of the multi-core m...

Disgrifiad llawn

Manylion Llyfryddiaeth
Prif Awduron:	NOAMI Ahmed, KUMAR PRADEEP Boya, SEKHAR PAIDIMARRY Chandra
Fformat:	Erthygl
Iaith:	English
Cyhoeddwyd:	Editura Universităţii din Oradea 2022-10-01
Cyfres:	Journal of Electrical and Electronics Engineering
Pynciau:	clock gating dynamic power ip cores multi-core system memory controller
Mynediad Ar-lein:	http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V15_N2_OCT_2022/NOAMI_JEEE.pdf

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