A study on flare minimisation in EUV lithography by post‐layout re‐allocation of wire segments
Abstract The feature size in Integrated Circuits (ICs) has been scaling down aggressively, thereby posing more challenges in their manufacturability. Conventional immersion lithography using a laser of 193 nm wavelength produces layouts having distortions that degrade performance significantly. To o...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi-IET
2021-07-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12028 |