A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS
This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is d...
Main Authors: | , , |
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Format: | Article |
Language: | English |
Published: |
MDPI AG
2022-02-01
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Series: | Electronics |
Subjects: | |
Online Access: | https://www.mdpi.com/2079-9292/11/5/705 |