The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Abstract The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state...

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Bibliographic Details
Main Authors: Wei Li, Hongxia Liu, Shulong Wang, Shupeng Chen, Qianqiong Wang
Format: Article
Language:English
Published: SpringerOpen 2017-09-01
Series:Nanoscale Research Letters
Subjects:
Tunneling FET (TFET)
DRAM
Programming optimization
Retention time
Online Access:http://link.springer.com/article/10.1186/s11671-017-2294-3

Internet

http://link.springer.com/article/10.1186/s11671-017-2294-3

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