The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
Abstract The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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SpringerOpen
2017-09-01
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| Series: | Nanoscale Research Letters |
| Subjects: | |
| Online Access: | http://link.springer.com/article/10.1186/s11671-017-2294-3 |
| _version_ | 1827850706325864448 |
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| author | Wei Li Hongxia Liu Shulong Wang Shupeng Chen Qianqiong Wang |
| author_facet | Wei Li Hongxia Liu Shulong Wang Shupeng Chen Qianqiong Wang |
| author_sort | Wei Li |
| collection | DOAJ |
| description | Abstract The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding “1”. The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading “1” to reading “0” (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM. |
| first_indexed | 2024-03-12T10:22:24Z |
| format | Article |
| id | doaj.art-2ba47ca1a49a426e8036cbcccdf57d22 |
| institution | Directory Open Access Journal |
| issn | 1931-7573 1556-276X |
| language | English |
| last_indexed | 2024-03-12T10:22:24Z |
| publishDate | 2017-09-01 |
| publisher | SpringerOpen |
| record_format | Article |
| series | Nanoscale Research Letters |
| spelling | doaj.art-2ba47ca1a49a426e8036cbcccdf57d222023-09-02T09:58:41ZengSpringerOpenNanoscale Research Letters1931-75731556-276X2017-09-011211810.1186/s11671-017-2294-3The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFETWei Li0Hongxia Liu1Shulong Wang2Shupeng Chen3Qianqiong Wang4Key Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian UniversityKey Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian UniversityKey Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian UniversityKey Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian UniversityKey Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian UniversityAbstract The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding “1”. The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading “1” to reading “0” (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.http://link.springer.com/article/10.1186/s11671-017-2294-3Tunneling FET (TFET)DRAMProgramming optimizationRetention time |
| spellingShingle | Wei Li Hongxia Liu Shulong Wang Shupeng Chen Qianqiong Wang The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET Nanoscale Research Letters Tunneling FET (TFET) DRAM Programming optimization Retention time |
| title | The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET |
| title_full | The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET |
| title_fullStr | The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET |
| title_full_unstemmed | The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET |
| title_short | The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET |
| title_sort | programming optimization of capacitorless 1t dram based on the dual gate tfet |
| topic | Tunneling FET (TFET) DRAM Programming optimization Retention time |
| url | http://link.springer.com/article/10.1186/s11671-017-2294-3 |
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