The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
Abstract The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
SpringerOpen
2017-09-01
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| Series: | Nanoscale Research Letters |
| Subjects: | |
| Online Access: | http://link.springer.com/article/10.1186/s11671-017-2294-3 |