103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth Noise
This paper presents a high-resolution, low-bandwidth, continuous-time delta-sigma modulator (CTDSM). Although continuous-time integrators are popular for implementing power-efficient DSMs, the coefficient of conventional RC integrators depends on the clock frequency and requires excessively large re...
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IEEE
2023-01-01
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Online Access: | https://ieeexplore.ieee.org/document/10258273/ |
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author | Hwaseong Shin Quanzhen Duan Jaedo Kim Sangwook Na Jeongjin Roh |
author_facet | Hwaseong Shin Quanzhen Duan Jaedo Kim Sangwook Na Jeongjin Roh |
author_sort | Hwaseong Shin |
collection | DOAJ |
description | This paper presents a high-resolution, low-bandwidth, continuous-time delta-sigma modulator (CTDSM). Although continuous-time integrators are popular for implementing power-efficient DSMs, the coefficient of conventional RC integrators depends on the clock frequency and requires excessively large resistance and capacitance for implementation in low-bandwidth CTDSMs. The high resistance causes thermal noise, limiting the overall performance of the modulator. Accordingly, the CTDSM presented herein incorporates a switched resistor (SR) integrator that overcomes the thermal noise issue and enables high-resolution CTDSM to be used in low-bandwidth applications. The proposed integrator also adopts a chopped negative-R technique to reduce the flicker noise in the amplifier while simultaneously enhancing linearity. The proposed 3rd-order CTDSM is successfully fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m CMOS process and achieves the following measurement results: a peak signal-to-noise and distortion ratio of 98.8 dB, dynamic range of 103.1 dB, total power consumption of <inline-formula> <tex-math notation="LaTeX">$20.3 \mu $ </tex-math></inline-formula> W, and signal bandwidth of 200 Hz. |
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issn | 2169-3536 |
language | English |
last_indexed | 2024-03-11T20:23:04Z |
publishDate | 2023-01-01 |
publisher | IEEE |
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spelling | doaj.art-2c8d829c5603406bb2ff87a98ebd14cd2023-10-02T23:00:36ZengIEEEIEEE Access2169-35362023-01-011110424410425210.1109/ACCESS.2023.331797510258273103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth NoiseHwaseong Shin0https://orcid.org/0000-0003-0285-3077Quanzhen Duan1https://orcid.org/0000-0003-0236-3019Jaedo Kim2https://orcid.org/0000-0002-5880-6213Sangwook Na3https://orcid.org/0009-0000-8743-0000Jeongjin Roh4https://orcid.org/0000-0001-6930-8183Department of Electrical Engineering, Hanyang University, Ansan, South KoreaSchool of Integrated Circuits, Sun Yat-sen University, Shenzhen, ChinaDepartment of Electrical Engineering, Hanyang University, Ansan, South KoreaDepartment of Electrical Engineering, Hanyang University, Ansan, South KoreaDepartment of Electrical Engineering, Hanyang University, Ansan, South KoreaThis paper presents a high-resolution, low-bandwidth, continuous-time delta-sigma modulator (CTDSM). Although continuous-time integrators are popular for implementing power-efficient DSMs, the coefficient of conventional RC integrators depends on the clock frequency and requires excessively large resistance and capacitance for implementation in low-bandwidth CTDSMs. The high resistance causes thermal noise, limiting the overall performance of the modulator. Accordingly, the CTDSM presented herein incorporates a switched resistor (SR) integrator that overcomes the thermal noise issue and enables high-resolution CTDSM to be used in low-bandwidth applications. The proposed integrator also adopts a chopped negative-R technique to reduce the flicker noise in the amplifier while simultaneously enhancing linearity. The proposed 3rd-order CTDSM is successfully fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m CMOS process and achieves the following measurement results: a peak signal-to-noise and distortion ratio of 98.8 dB, dynamic range of 103.1 dB, total power consumption of <inline-formula> <tex-math notation="LaTeX">$20.3 \mu $ </tex-math></inline-formula> W, and signal bandwidth of 200 Hz.https://ieeexplore.ieee.org/document/10258273/Analog-to-digital converter (ADC)switched resistor (SR) integratorcontinuous-time delta-sigma modulator (CTDSM)chopped negative Rlow bandwidth |
spellingShingle | Hwaseong Shin Quanzhen Duan Jaedo Kim Sangwook Na Jeongjin Roh 103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth Noise IEEE Access Analog-to-digital converter (ADC) switched resistor (SR) integrator continuous-time delta-sigma modulator (CTDSM) chopped negative R low bandwidth |
title | 103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth Noise |
title_full | 103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth Noise |
title_fullStr | 103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth Noise |
title_full_unstemmed | 103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth Noise |
title_short | 103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth Noise |
title_sort | 103 1 db dr switched resistor delta sigma modulator with chopped negative r for suppressing low bandwidth noise |
topic | Analog-to-digital converter (ADC) switched resistor (SR) integrator continuous-time delta-sigma modulator (CTDSM) chopped negative R low bandwidth |
url | https://ieeexplore.ieee.org/document/10258273/ |
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