GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning
This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection of circuit elements, the action masking scheme is employed. It also reduces the size of the action space leading to the impr...
Main Authors: | , , , |
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Format: | Article |
Language: | English |
Published: |
MDPI AG
2021-04-01
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Series: | Electronics |
Subjects: | |
Online Access: | https://www.mdpi.com/2079-9292/10/9/1032 |